Field of the Invention
The present invention relates to imaging apparatuses, and it particularly relates to an imaging apparatus having a signal processing circuit provided correspondingly to a column of a pixel array.
Description of the Related Art
A generally known imaging apparatus has a signal processing circuit for each column or a plurality of columns of a pixel array having an array of pixels in a matrix form and performs signal processing in parallel. The signal processing circuit performs processing such as Correlated Double Sampling (CDS) and offset adjustment, amplification, analog/digital conversion (A/D conversion) on signals output from pixels.
For example, Japanese Patent Laid-Open No. 2007-060036 discloses a method for supplying a drive signal that drives a plurality of signal processing circuits. According to Japanese Patent Laid-Open No. 2007-060036, buffer elements that transmit a drive signal are connected in series within a group of a plurality of signal processing circuits to reduce the peak current and the number of buffer elements.
However, the configuration described in Japanese Patent Laid-Open No. 2007-060036 has a buffer element for each signal processing circuit, which increases the number of buffer elements in proportional to the number of signal processing circuits. Moreover, the chip area increases when it is formed on a semiconductor substrate.
The delayed supply of a drive signal within a group of signal processing circuits may require the operation timing margin to be set longer. In other words, the operational speed is hard to increase.